Method to find a value within a range using weighted subranges

ABSTRACT

A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.

FIELD OF THE INVENTION

[0001] This invention relates to the field of information processing,and more particularly, to the matching of values in information systems.

BACKGROUND OF THE INVENTION

[0002] Information processing applications must often find a valuewithin a range of values. For example, a sorting system may organizediscrete units of information into groups defined by numericalboundaries. Before assigning each discrete unit of information to agroup, the relationship between each discrete unit of information andthe numerical boundaries must be established. Defining theserelationships often requires finding a value within a range of values.In some sorting systems, this is accomplished using a compute intensivesort algorithm in combination with a high performance microprocessor.Unfortunately, high performance microprocessors are expensive, andtherefore not suitable for use in products directed to the consumermarket.

[0003] An analog-to-digital (A/D) converter generates digital outputinformation related to analog input information. The conversion processassociated with one type of A/D converter requires manipulating discretepieces of information, the on and off states of resistor ladderswitches, in such a way that the final configuration of resistor ladderswitches matches a value within a range of values. Modem A/D convertersare designed to operate on a single chip and to function in a variety ofend user applications, such as cellular telephones and video games. Asingle A/D converter design may be required to function in anapplication that requires eight, twelve, sixteen or more bits ofresolution. Designers attempt to provide this flexibility in an A/Dconverter by providing an on chip microprocessor. Unfortunately, thesupplied microprocessor often has a limited instruction set, andoperates at a low frequency, so the requirements for applications thatmust operate at both high frequency and high resolution, such as quicklymatching a two byte value within a range of values, are difficult tomeet.

[0004] Some control systems seek to drive a difference signal, which isthe difference between an output information signal and an input signal,to zero in order to maintain a constant relationship between the inputsignal and the output information signal. This process of driving thedifference signal to zero may require the identification of a valuewithin a range of values.

[0005] In modem digital control systems, the control function is oftenperformed by a microprocessor. In some systems designed primarily forhigh reliability, such as systems designed for use in satellites, highfunction may also be required. High function microprocessors tend tofail more often than low function microprocessors, so it is difficult tomeet both requirements, and often a low function microprocessor isselected for a particular application. Unfortunately, the samealgorithms and software that accomplish tasks on a high functionmicroprocessor, such as identifying a value within a range of values, donot work on low function microprocessors.

[0006] For these and other reasons there is a need for the presentinvention.

SUMMARY OF THE INVENTION

[0007] The above-mentioned problems and other problems are addressed bythe present invention and will be understood by one skilled in the artupon reading and studying the following specification. A method offinding an unknown value from within a range of values is disclosed thatdivides the range into weighted subranges and then, beginning with anarbitrary search value within the range, performs a number of simplecomparisons to determine the value for each subrange that will result ina match with the target value. This method can also detect those caseswhere the target value lies outside the range.

[0008] In one embodiment, the method of finding an unknown value withina range of values is applied to impedance matching. In this embodiment,the output impedance of a pin on an integrated circuit is automaticallymatched to the impedance of the load connected to it. The output driverhas a controllable impedance that can be adjusted within a specificrange of impedances to match the external load impedance it is to drive.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is a flowchart of the general operation of the method offinding a value within range using weighted subranges.

[0010]FIG. 1A is a block diagram of one embodiment of an impedancematching system including a controllable impedance.

[0011]FIG. 1B is a block diagram of one embodiment of an impedancematching system including a variable impedance and a control system.

[0012]FIG. 2A is a diagram of a metal-oxide-semiconductor field-effecttransistor (MOSFET) suitable for use in connection with one embodimentof the present invention.

[0013]FIG. 2B is a graph of the drain-to-source conductance of a MOSFETsuitable for use as a variable impedance in one embodiment of thepresent invention.

[0014]FIG. 2C is a schematic diagram of a parallel connection ofserially connected resistor-transistor pairs suitable for use inconnection with one embodiment of the present invention.

[0015]FIG. 3 is a block diagram of a control system for use inconnection with one embodiment of the present invention.

[0016]FIG. 4A is part one of a flow chart of one embodiment of animpedance matching method.

[0017]FIG. 4B is part two of a flow chart of one embodiment of animpedance matching method.

DETAILED DESCRIPTION OF THE INVENTION

[0018] In the following detailed description of the invention, referenceis made to the accompanying drawings which form a part hereof, and inwhich are shown, by way of illustration, specific embodiments in whichthe invention may be practiced. The embodiments are intended to describeaspects of the invention in sufficient detail to enable those skilled inthe art to practice the invention. Other embodiments may be utilized andchanges may be made without departing from the scope of the presentinvention. The following detailed description is not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims.

GENERAL ALGORITHM DESCRIPTION

[0019] A method of finding an unknown value from within a range ofvalues operates by dividing the range into weighted subranges. Beginningwith an arbitrary search value within the range, the method performs anumber of simple comparisons to determine the value for each subrangethat will result in a match with the target value. This method can alsodetect those cases where the target value lies outside the range.

[0020] The first general step of the method is to define the allowablerange and the subranges that will be used. The subranges are definedsuch that higher order subranges represent some multiple of the nextlower order subrange. An example would be the use of the place order ofdigits in a number to define the subranges for ones, tens, hundreds,etc. In this example the ones subrange is the lowest order subrange andoffers the finest resolution. Each higher order subrange is a multipleof the subrange that precedes it, offering a reduction in resolution asa trade off for a larger step size for use in searching for the targetvalue. With the subranges defined, the unknown target becomes areference to compare the search value against.

[0021] Depending on the results of an initial comparison, the searchbranches to either of two paths to determine the correct value for thehighest order subrange needing adjustment in order to achieve a matchcondition. Upon successful completion of either path, a lower ordersubrange will be marked as the new highest order subrange for subsequentcomparisons and the search continues by branching to the other path. Thesearch alternates between the two paths until the lowest order subrangehas been adjusted and a match has been achieved.

[0022] In the first path, the search value is greater than or not lessthan the target value. Beginning with the lowest order subrange, thesubrange is set to its minimum value and the resulting new search valueis compared against the target value. This process is repeated with eachhigher order subrange until a) the highest subrange is reached or b) thesearch value is no longer greater than the target value. If the searchvalue is still greater than the target value when the highest ordersubrange is reached, then the highest order subrange is decrementeduntil the search value is no longer greater than the target value oruntil the highest order subrange reaches its minimum value, whicheveroccurs first. In either case, the highest order subrange has been set toits correct value. If the search value becomes less than or no longergreater than the target value, the next lower subrange is marked as thenew highest order subrange for subsequent comparisons and the searchbranches to a second path. If the search value becomes less than or nolonger greater than the target value before the highest order subrangeis reached, then all of the higher order subranges have been already setto their correct value. The subrange whose change caused the searchvalue to no longer be greater than the target value is marked as the newhighest order subrange and the search branches to the second path. Ifall subranges become set to their minimum values and the search value isstill greater than the target value then an underflow condition has beendetected and the search is ended.

[0023] In the second path, the search value is less than or not greaterthan the target value. Beginning with the lowest order subrange, set thesubrange to its maximum value and compare the resulting new search valueagainst the target. This process is repeated with each higher ordersubrange until a) the highest order subrange is reached or b) the searchvalue is greater than or no longer less than the target value. If thesearch value is still less than the target value when the highest ordersubrange is reached, then the highest order subrange is incrementeduntil either the search value is no longer less than the target value orthe highest order subrange reaches its maximum value. Either of thesestopping conditions is a result of the highest order subrange being setto its correct value. If the search value is no longer less than thetarget value, the next lower order subrange is marked as the new highestorder subrange and the search branches to the first path. If the searchvalue becomes greater than or not less than the target value before thehighest order subrange is reached, then the subrange whose change causedthis condition is marked as the new highest order subrange and thesearch branches to the first path. If all subranges become set to theirmaximum value and the search value is still less than the target value,then an overflow condition has been detected and the search is ended.

[0024] One embodiment of the algorithm 100 can generally be describedwith reference to FIG. 1. Initialization occurs at 102 where the lowestorder subrange index LOS is set equal to zero and the number ofsubranges N is selected. The highest order subrange index HOS is setequal to N−1, or one less than the number of subranges, in 104. Thesearch index i is set equal to the lowest order subrange index LOS at106.

[0025] A search value is compared to a target value at 108. If thesearch value is greater than the target value, then the search proceedsalong a first search path by comparing the search index i to the highestorder subrange index HOS at 130. If the search index i is not equal tothe highest order subrange index HOS, then the value of the subrangeindexed by i is set to its minimum value and the search index i isincremented at 132. The new search value resulting from the operation at132 is then compared to the target value at 134, and if the search valueis greater than the target value then the comparison at 130 is performedagain. The search will continue in this loop until the search index i isequal to the highest order subrange index HOS at or until the searchvalue is not greater than the target value at 134. If the search valueis not greater than the target value at 134, then the control flows to116 where the highest order subrange index HOS is set equal to thesearch index i.

[0026] If the search index i is equal to the highest order subrangeindex HOS at 130, then all the lower order subranges have been set totheir minimum values and it is necessary to decrease the value of thehighest order subrange until the search value is not greater than thetarget value. The search continues at 138 by comparing the value ofsubrange indexed by the search index i to its minimum value. If thevalue of the subrange is not equal to its minimum value, then the valueof the subrange is decremented at 140. The new search value resultingfrom the operation at 140 is compared to the target value at 142. If thesearch value is not greater than the target value at 142, then thecontrol flows back to the comparison at 138. If the search value is notgreater than the target value at 142 then the correct value for thesubrange indexed by the highest order subrange index HOS has been foundand the control flows to 126.

[0027] If the subrange indexed by the search value i is equal to itsminimum value at 138 then an underflow condition has been detected andthe control flows to 144. This underflow results from the followingconditions being met: 1) the highest order subrange being compared at138 equals its minimum value, 2) the lower order subranges all equaltheir minimum values, 3) the search value is greater than the targetvalue. Since the first two of these three conditions indicate that thesearch value is set to its minimum value, it is not possible to decreasethe search value further to make it match the target value. From thispoint control flows to 148.

[0028] Returning focus to the original comparison at 108, if the searchvalue is not greater than the target value, then the search proceedsalong a second search path by comparing the search index i to thehighest order subrange index HOS at 110. If the search index i is notequal to the highest order subrange index HOS, then the value of thesubrange indexed by i is set to its maximum value and the search index iis incremented at 112. The new search value resulting from the operationat 112 is then compared to the target value at 114, and if the searchvalue is not greater than the target value then the comparison at 110 isperformed again. The search will continue in this loop until the searchindex i is equal to the highest order subrange index HOS at 110 or untilthe search value is greater than the target value at 114. If the searchvalue is greater than the target value at 114, then the control flows to116 where the highest order subrange index HOS is set equal to thesearch index i.

[0029] If the search index i is equal to the highest order subrangeindex HOS at 110, then all the lower order subranges have been set totheir maximum values and it is necessary to increase the value of thehighest order subrange until the search value is greater than the targetvalue. The search continues at 118 by comparing the value of thesubrange indexed by the search index i to its maximum value. If thevalue of the subrange is not equal to its maximum value, then the valueof the subrange is incremented at 120. The new search value resultingfrom the operation at 120 is compared to the target value at 122. If thesearch value is not greater than the target value at 122, then thecontrol flows back to the comparison at 118. If the search value isgreater than the target value at 122 then the correct value for thesubrange indexed by the highest order subrange index HOS has been foundand the control flows to 126.

[0030] If the subrange indexed by the search value i is equal to itsmaximum value at 118 then an overflow condition has been detected andthe search control flows to 124. This overflow results from thefollowing conditions being met: 1) the highest order subrange beingcompared at 118 equals its maximum value, 2) the lower order subrangesall equal their maximum values, 3) the search value is not greater thanthe target value. Since the first two of these three conditions indicatethat the search value is set to its maximum value, it is not possible toincrease the search value further to make it match the target value.From this point control flows to 148.

[0031] In the comparison at 126, if the highest order subrange HOS andthe lowest order subrange index LOS are equal, then all the subrangeshave been set to the values that cause the search value to match thetarget value. From here the control flows to 148. If the highest ordersubrange index HOS does not equal the lowest order subrange index LOS at126, then it is necessary to continue the search to find the correctsetting for at least one lower order subrange. The control flows to 128where the search index i is decremented and the highest order subrangeindex HOS is set equal to this new value of i, indexing the next lowersubrange.

[0032] Setting the highest order subrange index HOS to a new value,either at 116 or at 128, marks the successful completion of the currentsearch path control flows to 106 where the search index i is set equalto the lowest order subrange index LOS. Following this the search valueis compared to the target value at 108. At the successful completion ofthe first path, the search value will not be greater than the targetvalue so the control flows to the second path at 110. Likewise, at thecompletion of the second path, the search value will be greater than thetarget value so the control flows to the first path at 130. Thus thesearch alternates between the two search paths until a solution isobtained.

[0033] Once a solution has been found, or an underflow or overflowcondition has been detected, control flows to 148. At this point theresults of the search are stored and control flows to 104 in preparationfor a new search to begin.

[0034] The embodiment described above has several advantages. First, itrapidly converges to the target value. Second, the individual operationsmap easily into the instruction set of inexpensive microprocessors,which makes this an attractive method of identifying a target value in arange of values in inexpensive consumer products.

[0035] The dynamic operation of one embodiment of a system embodying themethod of FIG. 1 and described above is best understood by studyingTables 1-4 that follow.

[0036] Tables 1-4 show in detail the progress through a system embodyingthe method illustrated in the flowchart of FIG. 1 for specific searchand target values. For example, in Table 1, the initial search value is4961 and the initial target value is 0375, and as can be seen thebeginning search value column the search starts with 4961 and ends with375, which is the last entry in the ending search value column.Similarly, for Table 2, the initial search value is 1756 and the targetvalue is 2104, for Table 3, the initial search value is 4961 and thetarget value is 375, and for Table 4, the initial search value is 1756and the target value is 5104. References to path #1 refer to the “yes”branch out of block 108, and references to path #2 refer to the “no”branch out of decision block 108. TABLE 1 Lowest Order Subrange (LOS)---ONES 2nd LOS (LOS+1)--- TENS 3rd LOS (LOS+2)--- HUNDREDS Highest OrderSubrange (HOS)--- THOUSANDS EXAMPLE #1 Initial Search Value > TargetValue Search Range: 0000-9999 Initial Search Value: 4961 Target Value:0375 Beginning Ending Search Search Value Value Comments Search >Target, branch to path #1 4961 4960 LOS set to min. 4960 4900 LOS +1 setto min. 4900 4000 LOS +2 set to min. 4000 3000 Dec HOS 3000 2000 Dec HOS2000 1000 Dec HOS 1000 0000 Dec HOS Search < Target, HOS found, LOS+2becomes new HOS, branch to path #2 0000 0009 LOS set to max. 0009 0099LOS+1 set to max. 0099 0199 Inc LOS+2 0199 0299 Inc LOS+2 0299 0399 IncLOS+2 Search > Target, LOS+2 found, LOS+1 becomes new HOS, branch topath #1 0399 0390 LOS set to min. 0390 0380 Dec LOS+1 0380 0370 DecLOS+1 Search < Target, LOS+1 found, LOS becomes new HOS, branch to path#2 0370 0371 Inc LOS 0371 0372 Inc LOS 0372 0373 Inc LOS 0373 0374 IncLOS 0374 0375 Inc LOS Search = Target, end.

[0037] TABLE 2 Lowest Order Subrange (LOS)--- ONES 2nd LOS (LOS+1)---TENS 3rd LOS (LOS+2)--- HUNDREDS Highest Order Subrange (HOS)---THOUSANDS EXAMPLE #2 Initial Search Value < Target Value Search Range:0000-9999 Initial Search Value: 1756 Target Value: 2104 Beginning EndingSearch Search Value Value Comments Search < Target, branch to path #21756 1759 LOS set to max. 1759 1799 LOS+1 set to max. 1799 1999 LOS+2set to max. 1999 2999 Inc HOS Search > Target, HOS found, LOS+1 becomesnew HOS, branch to path #1 2999 2990 LOS set to min. 2990 2900 LOS+1 setto min. 2900 2800 Dec LOS+2 2900 2700 Dec LOS+2 2900 2600 Dec LOS+2 29002500 Dec LOS+2 2900 2400 Dec LOS+2 2900 2300 Dec LOS+2 2900 2200 DecLOS+2 2900 2100 Dec LOS+2 Search < Target, LOS+2 found, LOS+1 becomesnew HOS, branch to path #2 2100 2109 LOS set to max. Search > Target,LOS+1 found, LOS becomes new HOS, branch to path #1 2109 2108 Dec LOS2108 2107 Dec LOS 2107 2106 Dec LOS 2106 2105 Dec LOS 2105 2104 Dec LOSSearch = Target, end.

[0038] TABLE 3 Lowest Order Subrange (LOS)--- ONES 2nd LOS (LOS+1)---TENS 3rd LOS (LOS+2)--- HUNDREDS Highest Order Subrange (HOS)---THOUSANDS EXAMPLE #3 Target Value < Min Range Value Search Range:1000-4999 Initial Search Value: 4961 Target Value: 0375 Beginning EndingSearch Search Value Value Comments Search > Target, branch to path #14961 4960 LOS set to min. 4960 4900 LOS+1 set to min. 4900 4000 LOS+2set to min. 4000 3000 Dec HOS 3000 2000 Dec HOS 2000 1000 Dec HOS Searchat bottom of range. Search > Target, UNDERFLOW, end.

[0039] TABLE 4 Lowest Order Subrange (LOS)--- ONES 2nd LOS (LOS+1)---TENS 3rd LOS (LOS+2)--- HUNDREDS Highest Order Subrange (HOS)---THOUSANDS EXAMPLE #4 Target Value > Max Range Value Search Range:1000-4999 Initial Search Value: 1756 Target Value: 5104 Beginning EndingSearch Search Value Value Comments Search < Target, branch to path #21756 1759 LOS set to max. 1759 1799 LOS+1 set to max. 1799 1999 LOS+2set to max. 1999 2999 Inc HOS 2999 3999 Inc HOS 3999 4999 Inc HOS Searchat top of range. Search < Target, OVERFLOW, end.

ONE EMBODIMENT OF THE GENERAL ALGORITHM TO IMPEDANCE MATCHING

[0040] The present invention has practical applications in many types ofelectronic systems. In one application, the present invention may beembodied in memory devices such as static random access memories(SRAM's), as part of a memory package such as single in line memorymodules (SIMM's) or dual in line memory modules (DIMM's). As additionalSIMM's or DIMM's are added to motherboards of computer systems, thecharacteristic impedance of the memory bus may change. The presentinvention allows for the adaptation to changes in the impedance on amemory bus when new memory is added to or removed from the bus bydynamically matching the bus driver impedance with the resulting busimpedance.

[0041] Referring to FIG. 1A, impedance matching system 1, in oneembodiment resent invention, comprises voltage source 5, first signalline 10, second signal line 20, and controllable impedance 25. Firstsignal line 10 is connected to second signal line 20, and controllableimpedance 25 is connected between voltage source 5 and first signal line10 and second signal line 20.

[0042] Signal line 10 and signal line 20 are transmission devicescapable of carrying electronic signals. For example, signal line 10 andsignal line 20 can be signal carrying lines in an integrated circuit ora memory device, a conductive wire, a wiring pattern on a system board,a strip line, or a coaxial cable. In addition, signal line 10 and signalline 20 need not be the same type of transmission device, nor need theyexist in the same electronic subsystem. For example, signal line 10 canbe a signal carrying line in an integrated circuit, while signal line 20can be a coaxial cable connected to the signal carrying line in theintegrated circuit.

[0043] Controllable impedance 25 is an electronic device having animpedance or a resistance that can be controlled. In one embodiment,controllable impedance 25 comprises a plurality of parallelresistor-transistor pairs. The parallel resistor-transistor pairs definea resistance ladder, and by switching on a transistor in one of theresistor-transistor pairs, a resistor is added to the resistance ladder.After the first resistor is added to the ladder, adding additionalresistors to the resistor ladder by turning on a transistor decreasesthe resistance of the controllable impedance. A parallel arrangement ofresistor-transistor pairs is shown in FIG. 2C and is described in moredetail below.

[0044] In an alternate embodiment, controllable impedance 25 comprises atransistor that has a controllable impedance or resistance. For example,a metal-oxide semiconductor (MOSFET) transistor is an electronic devicethat has a resistance that can be controlled.

[0045] Voltage source 5 can be selected to provide an appropriate valuefor controllable impedance 25. If controllable impedance 25 requires apositive voltage source to operate, then a positive voltage is selectedfor voltage source 5. If controllable impedance 25 requires a negativevoltage source to operate, then a negative voltage is selected forvoltage source 5. In addition voltage source 5 can be powered from asource of voltage, which is often referred to as a system voltage anddesignated as V_(CC) or V_(DD).

[0046] Impedance matching system 1 ensures that information signalsoriginating on signal line 10 are not reflected back along signal line10 as they are transmitted to signal line 20. Controllable impedance 25is dynamically changed to match the impedance of signal line 10 to theimpedance of signal line 20. This dynamic matching eliminatesreflections at the point where signal line 10 is connected to signalline 20.

AN ALTERNATE EMBODIMENT OF THE GENERAL ALGORITHM TO IMPEDANCE MATCHING

[0047] Referring to FIG. 1B, impedance matching system 100, in oneembodiment of the present invention, comprises V_(SOURCE) voltage 105,external pin 110 having a pin voltage and a pin circuit impedance, andsignal source 120 having signal source impedance 130, variable impedance140, and control system 150 having a first input port, a second inputport and an output port. Variable impedance 140 couples V_(SOURCE)voltage 105 to the external pin 110. The first input port of controlsystem 150 is coupled to V_(SOURCE) voltage 105, the second input portof control system 150 is coupled to external pin 110, and the outputsignal of control system 150 is coupled to variable impedance 140.Signal source 120 is also coupled to external pin 110. External pin 110may be an input pin, an output pin, or a bidirectional input-output(I/O) pin, which is suitable for use with a tristate device.

[0048] Variable impedance 140, in one embodiment of the presentinvention, is a metal-oxide-semiconductor field-effect transistor(MOSFET), which is controlled by the control system 150 to adjust theimpedance on input-output (I/O) pin 110. Both n-type and p-typemetal-oxide semiconductor field-effect transistors are suitable for usein connection with the present invention, and can be configured with anappropriate voltage source, either positive or negative. FIGS. 2A and 2Bshow a diagram of a MOSFET suitable for use in the present invention anda family of MOSFET curves showing drain current versus drain-to-sourcevoltage for various gate-to-source voltages. Those skilled in the artwill recognize that the voltage between the gate and source terminals ofa MOSFET can be used to control the impedance between the drain andsource terminals. For example, referring to FIG. 2A, MOSFET 200comprises gate terminal 205, source terminal 210, drain terminal 215,drain current, I_(D) 220, and drain-to-source voltage, V_(DS) 225, and avoltage between gate terminal 205 and source terminal 210 can controlthe impedance between drain terminal 215 and source terminal 210.

[0049] The relationship between the drain-to-source voltage, V_(DS) 225,and the drain current, I_(D) 220, of FIG. 2A, is shown in FIG. 2B. Graph230 in FIG. 2B comprises x-axis 235, y-axis 240, and a family ofconductance curves 245. X-axis 235 represents the drain-to-sourcevoltage, V_(DS) 225, and y-axis 240 represents the drain current, I_(D)220, for MOSFET 200 of FIG. 2A. A family of conductance curves 245 showsthe drain current, I_(D) 220, versus the drain-to-source voltage, V_(DS)225, for MOSFET 200 of FIG. 2A having a range of gate-to-sourcevoltages. Those skilled in the art will recognize that for MOSFET 200 ofFIG. 2A, the slope of each of the conductance curves in the family ofconductance curves 245 of FIG. 2B, can be varied by varying thegate-to-source voltage, and thereby changing the conductance between thedrain and source terminals of MOSFET 200. Using a MOSFET as a variableimpedance permits a broad range of impedance values to be easilyobtained.

[0050] Variable impedance 140, in an alternate embodiment of the presentinvention, is a parallel arrangement of serially connectedresistor-transistor pairs coupling V_(SOURCE) voltage 105 to externalpin 110. Those skilled in the art will recognize that the resistance ofthe parallel arrangement of the serially connected resistor-transistorpairs is controlled by switching each transistor on or off in order toeither include the resistor in the circuit or exclude the resistor fromthe circuit.

[0051] Referring to FIG. 2C, a parallel arrangement of a plurality-ofserially connected resistor-transistor pairs comprising transistor 250,transistor 255, resistor 260, and resistor 265 is shown. Also shown arecontrol lines 275, external pin 280, and internal input/output (I/O)signal 285. The transistor selected for use in each resistor-transistorpair is not critical to the practice of the invention. Any transistorcapable of functioning as a switch is suitable for use in practicing theinvention. The resistor value for each resistor-transistor pair isselected based on the impedances of the signal source in the system. Ifthe impedance of the signal source varies over a wide range of values,then a weighted set of resistor values is preferred. If the impedance ofthe signal source varies over a narrow range of values, then a set ofresistors having the same value is preferred.

[0052] Referring again to FIG. 1B, an advantage of using a parallelarrangement of serially connected resistor-transistor pairs is that theimpedance between the V_(SOURCE) voltage 105 and the external pin 110 iscapable of being digitally controlled, and a digitally controlledvariable impedance 140 is easily coupled to control system 150. Anotheradvantage of using a parallel arrangement of serially connectedresistor-transistor pairs is that variable impedance 140 can beimplemented in a variety of semiconductor technologies, since thetransistor is only required to function as a switch.

AN EMBODIMENT OF A CONTROL SYSTEM FOR USE WITH THE GENERAL ALGORITHM

[0053]FIG. 3 shows a block diagram of one embodiment of a control system300 suitable for use in the present invention. Control system 300comprises voltage reduction circuit 305, comparator 310, state logicsystem 315, coarse counter 320, and fine counter 325. Voltage reductioncircuit 305 receives V_(SOURCE) sense signal 330, which carries thevoltage V_(SOURCE) 105 of FIG. 1B. Comparator 310 receives an outputsignal from voltage reduction circuit 305 and external pin sense signal335, which carries the voltage present at external pin 110 of FIG. 1B.State logic system 315 receives an output signal from comparator 310, anoutput signal from course counter 320 and an output signal from finecounter 325. Coarse counter 320 and fine counter 325 receive outputsignals from state logic system 315. The output signals of coarsecounter 320 and fine counter 325 are combined to create control signal340, which can be used to increment or decrement the value of variableimpedance 140 of FIG. 1B. An embodiment of an algorithm that defines theoperation state logic system 315, coarse counter 320, and fine counter325 is shown in FIG. 4A and FIG. 4B.

[0054] Referring again to FIG. 1B, in operation control system 150 iscapable of sensing V_(SOURCE) voltage 105 and the pin voltage atexternal pin 110 and of driving variable impedance 140 to a value thatmaintains the pin voltage at external pin 110 at a value equal toone-half the value of V_(SOURCE) voltage 105. When control system 150achieves this result, the pin circuit impedance at external pin 110matches signal source impedance 130.

[0055] Referring again to FIG. 3, in operation state logic system 315generates count up and count down signals that are coupled to the inputport of coarse counter 320 and the input port of fine counter 325 inorder to generate control signal 340, which, when connected to variableimpedance 140 of FIG. 1B is capable of increasing and decreasingvariable impedance 140 of FIG. 1B. State logic system 315 responds tothe outputs of coarse counter 320, fine counter 325, and the output ofcomparator 310 to count up or count down coarse counter 320 and to countup or count down fine counter 325. In one embodiment, comparator 310generates an output signal that indicates to state logic system 315whether the output signal from voltage reduction circuit 305 is greaterthan or less than external pin sense signal 345. The speed of comparator310 is not critical to the practice of the present invention. Voltagereduction circuit 305, which in one embodiment can be a non-invertingamplifier, scales V_(SOURCE) sense signal 330 by a factor of one-half.The output signal of voltage reduction circuit 305 is coupled to aninput port of comparator 310.

[0056] Those skilled in the art will recognize that, in anotherembodiment of the present invention, a microprocessor can be substitutedfor state logic system 315, coarse counter 320, and fine counter 325.The flow diagram of FIG. 4A and FIG. 4B defines the operation of statelogic system 315 in combination with coarse counter 320 and fine counter325. This flow diagram can be reduced to a computer program, which canbe executed on a microprocessor. Since the flow diagram is composed of asmall number of simple comparisons and assignments arranged in tightloops, a microprocessor having small instruction set is suitable for usein the present invention.

AN EMBODIMENT OF THE GENERAL ALGORITHM USING COUNTERS

[0057] Referring to FIG. 4A and FIG. 4B, in one embodiment of thepresent invention, an impedance matching algorithm 400 defines thelogical operation of state logic system 315, coarse counter 320, andfine counter 325 of FIG. 3 or a microprocessor.

[0058] The operation of the flow diagram of FIG. 4A and FIG. 4B is bestunderstood by assuming values for the external pin voltage of FIG. 1B,V_(PIN), and the voltage source of FIG. 1B, V_(SOURCE) 105, which isdesignated as V_(CC), in FIG. 4A and FIG. 4B, and tracing a path throughthe flow diagram. Impedance matching algorithm 400 shown in FIG. 4A andFIG. 4B begins at decision block 410.

[0059] At decision block 410, V_(PIN) is compared to V_(CC/)2. If thepin voltage is greater than V_(CC)/2, then fine counter 325 is set tozero. If V_(PIN) is not greater than V_(CC)/2, then fine counter 325 isset to its maximum value.

[0060] Assuming that V_(PIN) is greater than V_(CC)/2, the algorithm isprepared to consider executing branch 415 and branch 420. For V_(PIN)greater than V_(CC)/2, the strategy of the algorithm in branch 415 andbranch 420 is to decrement coarse counter 320 until V_(PIN) is less thanV_(CC)/2, and to then increment fine counter 325 until V_(PIN) equalsV_(CC)/2. When V_(PIN) equals V_(CC)/2, the pin circuit impedancematches the signal source impedance. However, if after zeroing finecounter 325, V_(PIN) is not greater than V_(CC)/2, then coarse counter320 need not be adjusted and only fine counter 325 is adjusted,incremented until it reaches its maximum value or until V_(PIN) equalsV_(CC)/2.

[0061] Assuming that V_(PIN) is not greater than V_(CC)/2, the algorithmis prepared to consider executing branch 425 and branch 430. For V_(PIN)not greater than V_(CC)/2, the strategy of the algorithm in branch 425and branch 430 is to increment coarse counter 320 until V_(PIN) isgreater than V_(CC)/2 and to then decrement fine counter 325 untilV_(PIN) equals V_(CC)/2. When V_(PIN) equals V_(CC)/2, the pin circuitimpedance matches the signal source impedance. However, if after settingfine counter 325 to all ones, V_(PIN) is greater than V_(CC)/2, thencoarse counter 320 need not be adjusted and only fine counter 325 isadjusted, decremented until it reaches its minimum value or untilV_(PIN) equals V_(CC)/2.

CONCLUSION

[0062] The present invention has practical applications in many types ofelectronic systems. In one application, the present invention may beembodied in memory devices such as static random access memories(SRAM's), as part of a memory package such as single in line memorymodules (SIMM's) or dual in line memory modules (DIMM's). As additionalSIMM's or DIMM's are added to motherboards of computer systems, thecharacteristic impedance of the memory bus may change. The presentinvention allows for the adaptation to changes in the characteristicimpedance on a memory bus when new memory is added to or removed fromthe bus by dynamically matching the bus driver impedance with theresulting bus impedance.

[0063] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

What is claimed is:
 1. A method comprising: selecting a search valuehaving a plurality of subranges; selecting a target value; andrepeatedly altering at least one of the plurality of subranges until thesearch value matches the target value and storing the search value. 2.The method of claim 1, further comprising: repeatedly comparing thesearch value to the target value.
 3. The method of claim 2, whereinrepeatedly altering at least one of the plurality of subranges until thesearch value matches the target value comprises: incrementing anddecrementing the plurality of subranges in a counter until the searchvalue matches the target value.
 4. A method comprising: selecting asearch value having a plurality of subranges; selecting a target value;and repeatedly altering at least one of the plurality of subranges untilan underflow condition is detected and recording the underflowcondition.
 5. A method comprising: selecting a search value having aplurality of subranges; selecting a target value; and repeatedlyaltering at least one of the plurality of subranges until an overflowcondition is detected and recording the overflow condition.
 6. A systemcomprising: a counter unit representing a search value having aplurality of subranges; a register unit containing a target value; and acontrol unit operably coupled to the counter unit and the register unitand capable of repeatedly altering at least one of the plurality ofsubranges until a physically recordable condition selected from thegroup consisting of a match, an overflow, and an underflow occurs. 7.The system of claim 6, further comprising: a comparison unit operablycoupled to the counter unit and the register unit and the comparisonunit capable of repeatedly comparing the counter unit to the registerunit.
 8. An impedance matching circuit, comprising: a first signal line;a second signal line having a characteristic impedance and connected tothe first signal line; and a controllable impedance connected to thefirst signal line and the second signal line and operable fordynamically matching the characteristic impedance on the second signalline.
 9. The impedance matching circuit of claim 8, wherein thecontrollable impedance comprises a plurality of parallel resistorsarranged to provide discrete steps of impedance on the second signalline.
 10. The impedance matching circuit of claim 8, wherein thecontrollable impedance is a controlled transistor connected between thesecond signal line and a source of voltage.
 11. The impedance matchingcircuit of claim 10, wherein the source of voltage is positive.
 12. Theimpedance matching circuit of claim 10, wherein the source of voltage isnegative.
 13. The impedance matching circuit of claim 8, wherein thecontrollable impedance includes a circuit connected to the second signalline for sensing the characteristic impedance looking into the secondsignal line and for adjusting the controllable impedance in responsethereto.
 14. An impedance matching circuit, comprising: a internalsignal line; an external signal line having an impedance and connectedto the internal signal line; and a controllable impedance connectedbetween the external signal line and a power source and operable fordynamically matching the impedance on the external signal line.
 15. Theimpedance matching circuit of claim 14, wherein the controllableimpedance comprises: a plurality of switched resistors connected betweenthe power source and the external signal line; and a state machineoperable for switching selected ones of the plurality of switchedresistors.
 16. The impedance matching circuit of claim 14, wherein thecontrollable impedance comprises: a controlled transistor connectedbetween the external signal line and a source of voltage; and a controlcircuit connected to the controlled transistor and operable forcontrolling the impedance on the external signal line.
 17. The impedancematching circuit of claim 16, wherein the control circuit is connectedto the external signal line for sensing a first impedance looking intothe external signal line and dynamically changing the impedance lookingout of the external signal line.
 18. A dynamic impedance matchingcircuit, comprising: an internal signal line; an external pin connectedto the internal signal line; a controllable impedance device connectedbetween a voltage source and the external pin; and a control circuitconnected to the external pin and operable for sensing an impedancelooking out of the external pin and for controlling the controllableimpedance device to match the impedance.
 19. An impedance matchingsystem for an external pin on a integrated circuit, comprising: aninternal signal line connected to the external pin; a controllableimpedance circuit device connected between a voltage source and theexternal pin; and a control circuit connected to the external pin andoperable for sensing an impedance looking out of the external pin andfor controlling the controllable impedance device to match theimpedance.
 20. A variable resistance circuit for matching a reflectionfrom an external signal connected to a pin, comprising; an internalsignal connected to the pin; a controllable resistance connected betweenthe pin and a voltage source; and a sense circuit connected to thecontrollable resistance and the pin and operable for changing thecontrollable resistance to minimize the reflection.
 21. An impedancematching system, comprising: a variable impedance capable of coupling asource voltage to an external pin having a pin voltage and a pin circuitimpedance, and the external pin coupled to a signal source having asignal source impedance, the variable impedance is capable of matching apin circuit impedance to a signal source impedance; and a control systemcoupled to the variable impedance, to the source voltage, and to theexternal pin, the control system is capable of sensing the pin voltage,capable of sensing the source voltage, and capable of continuouslycontrolling the variable impedance in response to changes in the sourcevoltage and the pin voltage in order to control the pin voltage toone-half the source voltage.
 22. The impedance matching system of claim21, wherein the variable impedance is a metal-oxide semiconductor fieldeffect transistor (MOSFET) having a gate, a drain, and a source.
 23. Theimpedance matching system of claim 21, wherein the variable impedance isa resistor-transistor pair.
 24. The impedance matching system of claim21, wherein the signal source is a memory cell.
 25. The impedancematching system of claim 24, wherein the memory cell is included in amemory device.
 26. The impedance matching system of claim 25, whereinthe memory device is included in a system.
 27. An impedance matchingsystem, comprising: a variable impedance capable of coupling a sourcevoltage to an external pin having a pin circuit impedance and a signalsource having a signal source impedance coupled to the external pin, thevariable impedance is capable of matching the pin circuit impedance tothe signal source impedance; a voltage reduction circuit coupled to thesource voltage, the voltage reduction circuit is capable of generating aone-half source voltage; a comparator coupled to the pin voltage and theone-half source voltage, the comparator is capable of comparing the pinvoltage to the one-half source voltage; and a microprocessor capable ofcontinuously controlling the impedance of the variable impedance inorder to control the pin voltage to one-half the source voltage, themicroprocessor is coupled to the comparator and the variable impedance.28. The impedance matching system of claim 27, wherein the variableimpedance is a MOSFET having a gate, a drain, and a source.
 29. Theimpedance matching system of claim 27, wherein the variable impedance isa resistor-transistor pair.
 30. The impedance matching system of claim27, wherein the signal source is a memory cell.
 31. The impedancematching system of claim 30, wherein the memory cell is included in amemory device.
 32. The impedance matching system of claim 31, whereinthe memory device is included in a system.
 33. An impedance matchingsystem, comprising: a variable impedance capable of coupling a sourcevoltage to an external pin having a pin circuit impedance and a signalsource coupled to the external pin and the signal source having a signalsource impedance, the variable impedance is capable of matching the pincircuit impedance to the signal source impedance; a voltage reductioncircuit coupled to the source voltage, the voltage reduction circuit iscapable of generating a one-half source voltage; a comparator coupled tothe pin voltage and the voltage reduction circuit to receive theone-half source voltage, the comparator is capable of comparing the pinvoltage to the one-half source voltage; a coarse counter having a coarsecounter input port and a coarse counter output signal, the coarsecounter output signal is coupled to the variable impedance, and thecoarse counter is capable of increasing or decreasing the variableimpedance; a fine counter having a fine counter input port and a finecounter output signal, the fine counter output signal is coupled to thevariable impedance, and the fine counter is capable of increasing ordecreasing the variable impedance; and a state logic system coupled tothe comparator, the coarse counter output signal the fine counter outputsignal, the coarse counter input port, and the fine counter input port,the state logic system is capable of continuously controlling thevariable impedance in order to control the pin voltage to one-half thesource voltage.
 34. The impedance matching system of claim 33, whereinthe variable impedance is a MOSFET having a gate, a drain, and a source.35. The impedance matching system of claim 33, wherein the variableimpedance is a resistor-transistor pair.
 36. The impedance matchingsystem of claim 33, wherein the signal source is a memory cell.
 37. Theimpedance matching system of claim 36, wherein the memory cell isincluded in a memory device.
 38. The impedance matching system of claim37, wherein the memory device is included in a system.
 39. An impedancematching circuit, comprising: a circuit; a first signal line connectedto the circuit; a second signal line having a characteristic impedanceand connected to the first signal line; and a controllable impedanceconnected to the first signal line and the second signal line andoperable for dynamically matching the characteristic impedance on thesecond signal line.
 40. The impedance matching circuit of claim 39,wherein the controllable impedance comprises a plurality of parallelresistors arranged to provide discrete steps of impedance on the secondsignal line.
 41. The impedance matching circuit of claim 39, wherein thecontrollable impedance is a controlled transistor connected between thesecond signal line and a source of voltage.
 42. The impedance matchingcircuit of claim 41, wherein the source of voltage is positive.
 43. Theimpedance matching circuit of claim 41, wherein the source of voltage isnegative.
 44. The impedance matching circuit of claim 39, wherein thecontrollable impedance includes a circuit connected to the second signalline for sensing the characteristic impedance looking into the secondsignal line and for adjusting the controllable impedance in responsethereto.
 45. An impedance matching circuit, comprising: a circuit; ainternal signal line connected to the circuit; an external signal linehaving an impedance and connected to the internal signal line; and acontrollable impedance connected between the external signal line and apower source and operable for dynamically matching the impedance on theexternal signal line.
 46. The impedance matching circuit of claim 45,wherein the controllable impedance comprises: a plurality of switchedresistors connected between the power source and the external signalline; and a state machine operable for switching selected ones of theplurality of switched resistors.
 47. The impedance matching circuit ofclaim 45, wherein the controllable impedance comprises: a controlledtransistor connected between the external signal line and a source ofvoltage; and a control circuit connected to the controlled transistorand operable for controlling the impedance on the external signal line.48. The impedance matching circuit of claim 47, wherein the controlcircuit is connected to the external signal line for sensing a firstimpedance looking into the external signal line and dynamically changingthe impedance looking out of the external signal line.
 49. A dynamicimpedance matching circuit, comprising: a circuit; an internal signalline connected to the circuit; an external pin connected to the internalsignal line; a controllable impedance device connected between a voltagesource and the external pin; and a control circuit connected to theexternal pin and operable for sensing an impedance looking out of theexternal pin and for controlling the controllable impedance device tomatch the impedance.
 50. An impedance matching system for an externalpin on a integrated circuit, comprising: a circuit; an internal signalline connected to the external pin and to the circuit; an controllableimpedance circuit device connected between a voltage source and theexternal pin; and a control circuit connected to the external pin andoperable for sensing an impedance looking out of the external pin andfor controlling the controllable impedance device to match theimpedance.
 51. An impedance matching circuit, comprising: a memorydevice; a first signal line connected to the memory device; a secondsignal line having a characteristic impedance and connected to the firstsignal line; and a controllable impedance connected to the first signalline and the second signal line and operable for dynamically matchingthe characteristic impedance on the second signal line.
 52. Theimpedance matching circuit of claim 51, wherein the controllableimpedance comprises a plurality of parallel resistors arranged toprovide discrete steps of impedance on the second signal line.
 53. Theimpedance matching circuit of claim 51, wherein the controllableimpedance is a controlled transistor connected between the second signalline and a source of voltage.
 54. The impedance matching circuit ofclaim 53, wherein the source of voltage is positive.
 55. The impedancematching circuit of claim 53, wherein the source of voltage is negative.56. The impedance matching circuit of claim 51, wherein the controllableimpedance includes a circuit connected to the second signal line forsensing the characteristic impedance looking into the second signal lineand for adjusting the controllable impedance in response thereto.
 57. Animpedance matching circuit, comprising: a memory device; a internalsignal line connected to the memory device; an external signal linehaving an impedance and connected to the internal signal line; and acontrollable impedance connected between the external signal line and apower source and operable for dynamically matching the impedance on theexternal signal line.
 58. The impedance matching circuit of claim 57,wherein the controllable impedance comprises: a plurality of switchedresistors connected between the power source and the external signalline; and a state machine operable for switching selected ones of theplurality of switched resistors.
 59. The impedance matching circuit ofclaim 57, wherein the controllable impedance comprises: a controlledtransistor connected between the external signal line and a source ofvoltage; and a control circuit connected to the controlled transistorand operable for controlling the impedance on the external signal line.60. The impedance matching circuit of claim 59, wherein the controlcircuit is connected to the external signal line for sensing a firstimpedance looking into the external signal line and dynamically changingthe impedance looking out of the external signal line.
 61. A dynamicimpedance matching circuit, comprising: a memory device; an internalsignal line connected to the memory device; an external pin connected tothe internal signal line; a controllable impedance device connectedbetween a voltage source and the external pin; and a control circuitconnected to the external pin and operable for sensing an impedancelooking out of the external pin and for controlling the controllableimpedance device to match the impedance.
 62. An impedance matchingsystem for an external pin on a integrated circuit, comprising: a memorydevice; an internal signal line connected to the external pin and to thememory device; an controllable impedance circuit device connectedbetween a voltage source and the external pin; and a control circuitconnected to the external pin and operable for sensing an impedancelooking out of the external pin and for controlling the controllableimpedance device to match the impedance.
 63. An impedance matchingcircuit, comprising: an SRAM; a first signal line connected to the SRAM;a second signal line having a characteristic impedance and connected tothe first signal line; and a controllable impedance connected to thefirst signal line and the second signal line and operable fordynamically matching the characteristic impedance on the second signalline.
 64. The impedance matching circuit of claim 63, wherein thecontrollable impedance comprises a plurality of parallel resistorsarranged to provide discrete steps of impedance on the second signalline.
 65. The impedance matching circuit of claim 63, wherein thecontrollable impedance is a controlled transistor connected between thesecond signal line and a source of voltage.
 66. The impedance matchingcircuit of claim 65, wherein the source of voltage is positive.
 67. Theimpedance matching circuit of claim 65, wherein the source of voltage isnegative.
 68. The impedance matching circuit of claim 63, wherein thecontrollable impedance includes a circuit connected to the second signalline for sensing the characteristic impedance looking into the secondsignal line and for adjusting the controllable impedance in responsethereto.
 69. An impedance matching circuit, comprising: an SRAM; ainternal signal line connected to the SRAM; an external signal linehaving an impedance and connected to the internal signal line; and acontrollable impedance connected between the external signal line and apower source and operable for dynamically matching the impedance on theexternal signal line.
 70. The impedance matching circuit of claim 69,wherein the controllable impedance comprises: a plurality of switchedresistors connected between the power source and the external signalline; and a state machine operable for switching selected ones of theplurality of switched resistors.
 71. The impedance matching circuit ofclaim 69, wherein the controllable impedance comprises: a controlledtransistor connected between the external signal line and a source ofvoltage; and a control circuit connected to the controlled transistorand operable for controlling the impedance on the external signal line.72. The impedance matching circuit of claim 71, wherein the controlcircuit is connected to the external signal line for sensing a firstimpedance looking into the external signal line and dynamically changingthe impedance looking out of the external signal line.
 73. A dynamicimpedance matching circuit, comprising: an SRAM; an internal signal lineconnected to the SRAM; an external pin connected to the internal signalline; a controllable impedance device connected between a voltage sourceand the external pin; and a control circuit connected to the externalpin and operable for sensing an impedance looking out of the externalpin and for controlling the controllable impedance device to match theimpedance.
 74. An impedance matching system for an external pin on aintegrated circuit, comprising: an SRAM; an internal signal lineconnected to the external pin and to the SRAM; an controllable impedancecircuit device connected between a voltage source and the external pin;and a control circuit connected to the external pin and operable forsensing an impedance looking out of the external pin and for controllingthe controllable impedance device to match the impedance.
 75. Animpedance matching circuit, comprising: a motherboard; a first signalline connected to the motherboard; a second signal line having acharacteristic impedance and connected to the first signal line; and acontrollable impedance connected to the first signal line and the secondsignal line and operable for dynamically matching the characteristicimpedance on the second signal line.
 76. The impedance matching circuitof claim 75, wherein the controllable impedance comprises a plurality ofparallel resistors arranged to provide discrete steps of impedance onthe second signal line.
 77. The impedance matching circuit of claim 75,wherein the controllable impedance is a controlled transistor connectedbetween the second signal line and a source of voltage.
 78. Theimpedance matching circuit of claim 77, wherein the source of voltage ispositive.
 79. The impedance matching circuit of claim 77, wherein thesource of voltage is negative.
 80. The impedance matching circuit ofclaim 75, wherein the controllable impedance includes a circuitconnected to the second signal line for sensing the characteristicimpedance looking into the second signal line and for adjusting thecontrollable impedance in response thereto.
 81. An impedance matchingcircuit, comprising: a motherboard; an internal signal line coupled tothe motherboard; an external signal line having an impedance andconnected to the internal signal line; and a controllable impedanceconnected between the external signal line and a power source andoperable for dynamically matching the impedance on the external signalline.
 82. The impedance matching circuit of claim 81, wherein thecontrollable impedance comprises: a plurality of switched resistorsconnected between the power source and the external signal line; and astate machine operable for switching selected ones of the plurality ofswitched resistors.
 83. The impedance matching circuit of claim 81wherein the controllable impedance comprises: a controlled transistorconnected between the external signal line and a source of voltage; anda control circuit connected to the controlled transistor and operablefor controlling the impedance on the external signal line.
 84. Theimpedance matching circuit of claim 83, wherein the control circuit isconnected to the external signal line for sensing a first impedancelooking into the external signal line and dynamically changing theimpedance looking out of the external signal line.
 85. A dynamicimpedance matching circuit, comprising: a motherboard; an internalsignal line coupled to the motherboard; an external pin connected to theinternal signal line; a controllable impedance device connected betweena voltage source and the external pin; and a control circuit connectedto the external pin and operable for sensing an impedance looking out ofthe external pin and for controlling the controllable impedance deviceto match the impedance.
 86. An impedance matching system for an externalpin on a integrated circuit, comprising: a motherboard; an internalsignal line connected to the external pin and to the motherboard; ancontrollable impedance circuit device connected between a voltage sourceand the external pin; and a control circuit connected to the externalpin and operable for sensing an impedance looking out of the externalpin and for controlling the controllable impedance device to match theimpedance.
 87. An impedance matching system, comprising: a variableimpedance capable of coupling a source voltage to an external pin havinga pin voltage and a pin circuit impedance, and the external pin coupledto a circuit signal source having a circuit signal source impedance, thevariable impedance is capable of matching a pin circuit impedance to asignal source impedance; and a control system coupled to the variableimpedance, to the source voltage, and to the external pin, the controlsystem is capable of sensing the pin voltage, capable of sensing thesource voltage, and capable of continuously controlling the variableimpedance in response to changes in the source voltage and the pinvoltage in order to control the pin voltage to one-half the sourcevoltage.
 88. The impedance matching system of claim 87, wherein thevariable impedance is a MOSFET having a gate, a drain, and a source. 89.The impedance matching system of claim 87, wherein the variableimpedance is a resistor-transistor pair.
 90. An impedance matchingsystem, comprising: a variable impedance capable of coupling a sourcevoltage to an external pin having a pin circuit impedance and a circuitsignal source having a circuit signal source impedance coupled to theexternal pin, the variable impedance is capable of matching the pincircuit impedance to the signal source impedance; a voltage reductioncircuit coupled to the source voltage, the voltage reduction circuit iscapable of generating a one-half source voltage; a comparator coupled tothe pin voltage and the one-half source voltage, the comparator iscapable of comparing the pin voltage to the one-half source voltage; anda microprocessor capable of continuously controlling the impedance ofthe variable impedance in order to control the pin voltage to one-halfthe source voltage, the microprocessor is coupled to the comparator andthe variable impedance.
 91. The impedance matching system of claim 90,wherein the variable impedance is a MOSFET having a gate, a drain, and asource.
 92. The impedance matching system of claim 90, wherein thevariable impedance is a resistor-transistor pair.
 93. An impedancematching system, comprising: a variable impedance capable of coupling asource voltage to an external pin having a pin circuit impedance and acircuit signal source coupled to the external pin and the circuit signalsource having a circuit signal source impedance, the variable impedanceis capable of matching the pin circuit impedance to the circuit signalsource impedance; a voltage reduction circuit coupled to the sourcevoltage, the voltage reduction circuit is capable of generating aone-half source voltage; a comparator coupled to the pin voltage and thevoltage reduction circuit to receive the one-half source voltage, thecomparator is capable of comparing the pin voltage to the one-halfsource voltage; a coarse counter having a coarse counter input port anda coarse counter output signal, the coarse counter output signal iscoupled to the variable impedance, and the coarse counter is capable ofincreasing or decreasing the variable impedance; a fine counter having afine counter input port and a fine counter output signal, the finecounter output signal is coupled to the variable impedance, and the finecounter is capable of increasing or decreasing the variable impedance;and a state logic system coupled to the comparator, the coarse counteroutput signal the fine counter output signal, the coarse counter inputport, and the fine counter input port, the state logic system is capableof continuously controlling the variable impedance in order to controlthe pin voltage to one-half the source voltage.
 94. The impedancematching system of claim 93, wherein the variable impedance is a MOSFEThaving a gate, a drain, and a source.
 95. The impedance matching systemof claim 93, wherein the variable impedance is a resistor-transistorpair.
 96. An impedance matching system, comprising: a variable impedancecapable of coupling a source voltage to an external pin having a pinvoltage and a pin circuit impedance, and the external pin coupled to amemory signal source having a memory signal source impedance, thevariable impedance is capable of matching a pin circuit impedance to thememory signal source impedance; and a control system coupled to thevariable impedance, to the source voltage, and to the external pin, thecontrol system is capable of sensing the pin voltage, capable of sensingthe source voltage, and capable of continuously controlling the variableimpedance in response to changes in the source voltage and the pinvoltage in order to control the pin voltage to one-half the sourcevoltage.
 97. The impedance matching system of claim 96, wherein thevariable impedance is a MOSFET having a gate, a drain, and a source. 98.The impedance matching system of claim 96, wherein the variableimpedance is a resistor-transistor pair.
 99. An impedance matchingsystem, comprising: a variable impedance capable of coupling a sourcevoltage to an external pin having a pin circuit impedance and a memorysignal source having a memory signal source impedance coupled to theexternal pin, the variable impedance is capable of matching the pincircuit impedance to the memory signal source impedance; a voltagereduction circuit coupled to the source voltage, the voltage reductioncircuit is capable of generating a one-half source voltage; a comparatorcoupled to the pin voltage and the one-half source voltage, thecomparator is capable of comparing the pin voltage to the one-halfsource voltage; and a microprocessor capable of continuously controllingthe impedance of the variable impedance in order to control the pinvoltage to one-half the source voltage, the microprocessor is coupled tothe comparator and the variable impedance.
 100. The impedance matchingsystem of claim 99, wherein the variable impedance is a MOSFET having agate, a drain, and a source.
 101. The impedance matching system of claim99, wherein the variable impedance is a resistor-transistor pair. 102.An impedance matching system, comprising: a variable impedance capableof coupling a source voltage to an external pin having a pin circuitimpedance and a memory signal source coupled to the external pin and thememory signal source having a memory signal source impedance, thevariable impedance is capable of matching the pin circuit impedance tothe memory signal source impedance; a voltage reduction circuit coupledto the source voltage, the voltage reduction circuit is capable ofgenerating a one-half source voltage; a comparator coupled to the pinvoltage and the voltage reduction circuit to receive the one-half sourcevoltage, the comparator is capable of comparing the pin voltage to theone-half source voltage; a coarse counter having a coarse counter inputport and a coarse counter output signal, the coarse counter outputsignal is coupled to the variable impedance, and the coarse counter iscapable of increasing or decreasing the variable impedance; a finecounter having a fine counter input port and a fine counter outputsignal, the fine counter output signal is coupled to the variableimpedance, and the fine counter is capable of increasing or decreasingthe variable impedance; and a state logic system coupled to thecomparator, the coarse counter output signal the fine counter outputsignal, the coarse counter input port, and the fine counter input port,the state logic system is capable of continuously controlling thevariable impedance in order to control the pin voltage to one-half thesource voltage.
 103. The impedance matching system of claim 102, whereinthe variable impedance is a MOSFET having a gate, a drain, and a source.104. The impedance matching system of claim 102, wherein the variableimpedance is a resistor-transistor pair.
 105. An impedance matchingsystem, comprising: a variable impedance capable of coupling a sourcevoltage to an external pin having a pin voltage and a pin circuitimpedance, and the external pin coupled to an SRAM signal source havingan SRAM signal source impedance, the variable impedance is capable ofmatching a pin circuit impedance to the SRAM signal source impedance;and a control system coupled to the variable impedance, to the sourcevoltage, and to the external pin, the control system is capable ofsensing the pin voltage, capable of sensing the source voltage, andcapable of continuously controlling the variable impedance in responseto changes in the source voltage and the pin voltage in order to controlthe pin voltage to one-half the source voltage.
 106. The impedancematching system of claim 105, wherein the variable impedance is a MOSFEThaving a gate, a drain, and a source.
 107. The impedance matching systemof claim 105, wherein the variable impedance is a resistor-transistorpair.
 108. An impedance matching system, comprising: a variableimpedance capable of coupling a source voltage to an external pin havinga pin circuit impedance and an SRAM signal source having a SRAM signalsource impedance coupled to the external pin, the variable impedance iscapable of matching the pin circuit impedance to the SRAM signal sourceimpedance; a voltage reduction circuit coupled to the source voltage,the voltage reduction circuit is capable of generating a one-half sourcevoltage; a comparator coupled to the pin voltage and the one-half sourcevoltage, the comparator is capable of comparing the pin voltage to theone-half source voltage; and a microprocessor capable of continuouslycontrolling the impedance of the variable impedance in order to controlthe pin voltage to one-half the source voltage, the microprocessor iscoupled to the comparator and the variable impedance.
 109. The impedancematching system of claim 108, wherein the variable impedance is a MOSFEThaving a gate, a drain, and a source.
 110. The impedance matching systemof claim 108, wherein the variable impedance is a resistor-transistorpair.
 111. An impedance matching system, comprising: a variableimpedance capable of coupling a source voltage to an external pin havinga pin circuit impedance and an SRAM signal source coupled to theexternal pin and the SRAM signal source having an SRAM signal sourceimpedance, the variable impedance is capable of matching the pin circuitimpedance to the SRAM signal source impedance; a voltage reductioncircuit coupled to the source voltage, the voltage reduction circuit iscapable of generating a one-half source voltage; a comparator coupled tothe pin voltage and the voltage reduction circuit to receive theone-half source voltage, the comparator is capable of comparing the pinvoltage to the one-half source voltage; a coarse counter having a coarsecounter input port and a coarse counter output signal, the coarsecounter output signal is coupled to the variable impedance, and thecoarse counter is capable of increasing or decreasing the variableimpedance; a fine counter having a fine counter input port and a finecounter output signal, the fine counter output signal is coupled to thevariable impedance, and the fine counter is capable of increasing ordecreasing the variable impedance; and a state logic system coupled tothe comparator, the coarse counter output signal the fine counter outputsignal, the coarse counter input port, and the fine counter input port,the state logic system is capable of continuously controlling thevariable impedance in order to control the pin voltage to one-half thesource voltage.
 112. The impedance matching system of claim 111, whereinthe variable impedance is a MOSFET having a gate, a drain, and a source.113. The impedance matching system of claim 111, wherein the variableimpedance is a resistor-transistor pair.
 114. A method comprising:sensing a source voltage and a pin circuit voltage at an external pin;and continuously controlling a variable impedance, connected to thesource voltage and the external pin, in response to the source voltageand the pin circuit voltage to maintain the pin circuit voltage atone-half the source voltage.
 115. The method of claim 114, whereinsensing a source voltage and a pin circuit voltage at an external pincomprises: sensing the source voltage with a voltage reduction circuit;and sensing the pin circuit voltage with a comparator.
 116. The methodof claim 114, wherein continuously controlling a variable impedance,connected to the source voltage and the external pin, in response to thesource voltage and the pin circuit voltage to maintain the pin circuitvoltage at one-half the source voltage comprises: receiving a digitalcomparison signal; and digitally generating a control signal forcontinuously controlling the variable impedance.
 117. A methodcomprising: comparing a pin circuit voltage at an external pin toone-half of a source voltage to generate a comparison signal; andcontinuously controlling a variable impedance, connected to the sourcevoltage and the external pin, in response to the comparison signal tomaintain the pin circuit voltage at one-half the source voltage. 118.The method of claim 117, continuously controlling a variable impedance,connected to the source voltage and the external pin, in response to thecomparison signal to maintain the pin circuit voltage at one-half thesource voltage comprises: receiving a digital comparison signal; anddigitally generating a control signal for continuously controlling thevariable impedance.
 119. A method comprising: sensing a source voltage;generating a voltage signal that is one-half the source voltage;comparing a pin circuit voltage signal to the voltage signal to generatea comparison signal; adjusting a coarse counter having an output signalin response to the comparison signal; adjusting a fine counter having anoutput signal in response to the comparison signal; and controlling avariable impedance with the output signal of the coarse counter and theoutput signal of the fine counter to drive the pin circuit voltagesignal to the generated voltage signal.
 120. A method comprising:sensing a source voltage; generating a voltage signal that is one-halfthe source voltage; comparing a pin circuit voltage signal to thevoltage signal to generate a comparison signal; adjusting a coarsecounter variable having a value in response to the comparison signal;adjusting a fine counter variable having a value in response to thecomparison signal; and controlling a variable impedance with the valueof the coarse counter variable and the value of the fine countervariable to drive the pin circuit voltage signal to the generatedvoltage signal.
 121. A method comprising: comparing a pin circuitvoltage to one-half of a source voltage to determine whether the pincircuit voltage is initially less than one-half of the source voltage;incrementing a coarse counter to a value greater than one-half of thesource voltage, when the pin circuit voltage is initially less thanone-half of the source voltage; decrementing a fine counter until thevalue of the coarse counter and the fine counter equals one-half of thesource voltage, when the pin circuit voltage is initially less thanone-half of the source voltage; decrementing the coarse counter to avalue less than the pin circuit voltage, when the pin circuit voltage isinitially greater than one-half of the source voltage; and incrementingthe fine counter until the value of the coarse counter and the finecounter equals one-half of the source voltage, when the pin circuitvoltage is initially greater than one-half of the source voltage.
 122. Amethod comprising: comparing a pin circuit voltage to one-half of asource voltage to determine whether the pin circuit voltage is initiallyless than one-half of the source voltage; incrementing a coarse countervariable to a value greater than one-half of the source voltage, whenthe pin circuit voltage is initially less than one-half of the sourcevoltage; decrementing a fine counter variable until the value of thecoarse counter variable and the fine counter variable equals one-half ofthe source voltage, when the pin circuit voltage is initially less thanone-half of the source voltage; decrementing the coarse counter variableto a value less than-the pin circuit voltage, when the pin circuitvoltage is initially greater than one-half of the source voltage; andincrementing the fine counter variable until the value of the coarsecounter variable and the fine counter variable equals one-half of thesource voltage, when the pin circuit voltage is initially greater thanone-half of the source voltage.
 123. A method for matching a searchvalue to a target value in a range of values having a maximum value anda minimum value, in a system having a coarse counter and a fine counterrepresenting the search value, the method comprising: comparing thesearch value to the target value to determine whether the search valueis initially less than the target value; incrementing the coarse counterto a value greater than the target value, when the search value isinitially less than the target value; decrementing the fine counteruntil the value of the coarse counter and the fine counter equals thetarget value, when the search value is initially less than the targetvalue; decrementing the coarse counter to a value less than the targetvalue, when the search value is initially not less than the targetvalue; and incrementing the fine counter until the value of the coarsecounter and the fine counter equals the target value, when the searchvalue is initially not less than the target value.